1. Field of the Invention
The present invention relates to a semiconductor device, a method of manufacturing a semiconductor device, an SRAM device and a method of manufacturing an SRAM device. More particularly, the present invention relates to a semiconductor device, a method of manufacturing a semiconductor device, an SRAM device and a method of manufacturing an SRAM device having a sufficient process margin.
2. Description of the Related Art
Generally, semiconductor memory devices may be categorized as either a dynamic random access memory (DRAM) device or a static random access memory (SRAM) device in accordance with memory type. The SRAM device has a rapid speed, low power consumption, and a simply operated structure. Accordingly, the SRAM device is currently noticed in a semiconductor memory field. Information stored in the DRAM device is periodically refreshed. A periodical refresh of information stored in the SRAM device is, however, not necessary.
A typical SRAM device includes two pull-down elements, two pass elements, and two pull-up elements. The SRAM device may be classified as either a full CMOS type, a high load resistor (HLR) type, or a thin film transistor (TFT) type in accordance with the configuration of the pull-up element. A p-channel bulk MOSFET is used as the pull-up element in the full CMOS type. A polysilicon layer having a high resistance value is used as the pull-up element in the HLR type. A p-channel polysilicon TFT is used as the pull-up element in the TFT type. The SRAM device having the full CMOS type of a cell has a low standby current, and also stably operates compared to the SRAM having other types of cells. FIG. 1 is a circuit illustrating a conventional full CMOS type SRAM cell.
Referring to FIG. 1, a conventional SRAM cell includes first and second pass transistors Q1 and Q2 for electrically connecting first and second bit lines BL1 and BL2 to first and second memory cell nodes Nd1 and Nd2, respectively, a PMOS type pull-up transistor Q5 electrically connected between the first memory cell node Nd1 and a positive supply voltage Vdd, and an NMOS type pull-down transistor Q3 electrically connected between the first memory cell node Nd1 and a negative supply voltage Vss. The PMOS type pull-up transistor Q5 and the NMOS type pull-down transistor Q3 are controlled by a signal outputted from the second memory cell node Nd2 to thereby provide the positive supply voltage Vdd or the negative supply voltage Vss to the first memory cell node Nd1.
The conventional SRAM cell further includes a PMOS type pull-up transistor Q6 electrically connected between the positive supply voltage Vdd and the second memory cell node Nd2, and an NMOS type pull-down transistor Q4 electrically connected between the second memory node Nd2 and the negative supply voltage Vss. The PMOS type pull-up transistor Q6 and the NMOS type pull-down transistor Q4 are controlled by a signal outputted from the first memory cell node Nd1 to thereby provide the positive supply voltage Vdd or the negative supply voltage Vss to the second memory cell node Nd2.
The first pass transistor Q1, the NMOS type pull-down transistor Q3 and the PMOS pull-up transistor Q5 are interconnected at the first memory cell node Nd1. The second pass transistor Q2, the NMOS type pull-down transistor Q4 and the PMOS pull-up transistor Q6 are interconnected at the second memory cell node Nd2.
The full CMOS type SRAM cell includes the NMOS type transistors Q1, Q2, Q3 and Q4, and the PMOS type transistors Q5 and Q6. When the NMOS and PMOS type transistors are disposed adjacently to each other in one cell, a latch-up and the like may occur, which causes an excessive current to flow between a positive supply voltage line and a negative supply voltage line.
To prevent the occurrence of the latch-up, active patterns are disposed so that pitches between the active patterns can have more than two sizes. Namely, in such arrangement of the active patterns, a pitch between an active pattern in which the PMOS type transistor is formed and an active pattern in which the NMOS type transistor is formed is relatively lengthencd to perform an entirely elemental isolation between the PMOS and NMOS transistors. On the contrary, a pitch between active patterns in which identical MOS type transistors are disposed is relatively shortened.
Thus, in the conventional full CMOS type SRAM cell, since the pitches between the active patterns have more than two sizes that are different from each other, pitches between patterns and pitches between contacts formed on the active pattern, respectively, are also more than two sizes. When the pitches between the patterns formed by the same process are varied as described above, a margin of a photolithography process for forming the patterns is determined based on the minimal one of the pitches between the patterns. Accordingly, the process margin is greatly decreased so that a probability of failures in forming the patterns may be high. Furthermore, it may be difficult to manufacture a highly-integrated semiconductor device by shrinking a cell size of the semiconductor device.
Embodiments of the invention address these and other disadvantages of the conventional art.